
30
4109LS–8051–02/08
AT8xC51SND1C
7.4.0.5
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 33. SPI Interface Master AC Timing
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Note:
1. Value of this parameter depends on software.
Symbol
Parameter
Min
Max
Unit
Slave Mode
T
CHCH
Clock Period
2
T
PER
T
CHCX
Clock High Time
0.8
T
PER
T
CLCX
Clock Low Time
0.8
T
PER
T
SLCH, TSLCL
SS Low to Clock edge
100
ns
T
IVCL, TIVCH
Input Data Valid to Clock Edge
40
ns
T
CLIX, TCHIX
Input Data Hold after Clock Edge
40
ns
T
CLOV, TCHOV
Output Data Valid after Clock Edge
40
ns
T
CLOX, TCHOX
Output Data Hold Time after Clock Edge
0
ns
T
CLSH, TCHSH
SS High after Clock Edge
0
ns
T
SLOV
SS Low to Output Data Valid
50
ns
T
SHOX
Output Data Hold after SS High
50
ns
T
SHSL
SS High to SS Low
(1)
T
ILIH
Input Rise Time
2
s
T
IHIL
Input Fall Time
2
s
T
OLOH
Output Rise time
100
ns
T
OHOL
Output Fall Time
100
ns
Master Mode
T
CHCH
Clock Period
2
T
PER
T
CHCX
Clock High Time
0.8
T
PER
T
CLCX
Clock Low Time
0.8
T
PER
T
IVCL, TIVCH
Input Data Valid to Clock Edge
20
ns
T
CLIX, TCHIX
Input Data Hold after Clock Edge
20
ns
T
CLOV, TCHOV
Output Data Valid after Clock Edge
40
ns
TCLOX, TCHOX
Output Data Hold Time after Clock Edge
0
ns
TILIH
Input Data Rise Time
2
s
TIHIL
Input Data Fall Time
2
s
TOLOH
Output Data Rise time
50
ns
TOHOL
Output Data Fall Time
50
ns